View M37516M6-A05_2929965.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge mitsubishi electric corporation spec.name customer's std.spec prepared by checked by approved by date r e v integrated circuit 1. type no. m37516m6-xxxhp 2. function single chip 8-bit microcomputer 3. application office automation,household products etc. 4. outline 4.1 name 48p6d / 48p6q (48pin 0.5mm pitch plastic-molded lqfp) 4.2 drawing no. 5. circuit drawing no. 6. pin configuration see page 2 7. related documents h.yamazoe y.hayashi m.abe 31 may '99
2/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge description the m37516m6-xxxhp is the 8-bit microcomputer based on the 740 family core technology. the m37516m6-xxxhp is designed for the household products and office automation equipment and includes serial i/o functions, 8-bit timer, a-d converter, and i 2 c-bus interface. features l basic machine-language instructions ...................................... 71 l minimum instruction execution time ................................... 0.5us (at 8 mhz oscillation frequency) l memory size rom ............................................................................. 24 kbytes ram .............................................................................. 640 bytes l programmable input/output ports ............................................ 40 l interrupts ................................................. 17 sources, 16 vectors l timers ............................................................................. 8-bit 5 4 l serial i/o1 .................... 8-bit 5 1(uart or clock-synchronized) l serial i/o2 ................................... 8-bit 5 1(clock-synchronized) l multi-master i 2 c-bus interface (option) ....................... 1 channel l pwm ............................................................................... 8-bit 5 1 l a-d converter ............................................... 10-bit 5 8 channels l watchdog timer ............................................................ 16-bit 5 1 pin configuration (top view) fig. 1 m37516m6-xxxhp pin configuration l clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) l power source voltage in high-speed mode .................................................. 4.0 to 5.5 v (at 8 mhz oscillation frequency) in high-speed mode .................................................. 2.7 to 5.5 v (at 4 mhz oscillation frequency) in middle-speed mode ............................................... 2.7 to 5.5 v (at 8 mhz oscillation frequency) in low-speed mode .................................................... 2.7 to 5.5 v (at 32 khz oscillation frequency) l power dissipation in high-speed mode .......................................................... 34 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode .............................................................. 60uw (at 32 khz oscillation frequency, at 3 v power source voltage) l operating temperature range .................................... C20 to 85 c application office automation equipment, fa equipment, household products, consumer electronics, etc. package type : 48p6d-a / 48p6q-a (48-pin plastic-molded lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 48 47 46 45 44 43 42 41 40 39 p0 2 /s clk2 p0 1 /s out2 p0 0 /s in2 p3 7 /an 7 p3 6 /an 6 p0 6 p0 5 p0 4 p0 3 /s rdy2 m37516m6-xxxhp p3 1 /an 1 av ss p4 7 p3 3 /an 3 v cc p1 7 (led 7 ) v ss p2 6 /s clk p2 5 /scl 2 /t x d p2 4 /sda 2 /r x d p2 3 /scl 1 cnv ss p2 1 /x cin p4 2 /int 1 p4 1 /int 0 p4 0 /cntr 1 p2 7 /cntr 0 /s rdy1 p2 2 /sda 1 p1 4 (led 4 ) p1 5 (led 5 ) x in p1 6 (led 6 ) x out p2 0 /x cout p0 7 p1 0 (led 0 ) p3 2 /an 2 v ref p3 0 /an 0 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm p4 6 p4 5 14 23 p1 3 (led 3 ) 24 reset p1 2 (led 2 ) p1 1 (led 1 ) 38 p3 4 /an 4 37 p3 5 /an 5
3/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge functional block diagram fig. 2 functional block diagram functional block int 0 C cntr 0 cntr 1 v ref av ss r a m r o m c p u a x y s pc h pc l ps v ss 18 reset 15 v cc 43 12 cnv ss 44 45 x in 16 17 si/o1(8) reset input clock generating circuit main-clock input main-clock output a-d converter (10) timer y( 8 ) timer x( 8 ) prescaler 12(8) prescaler x(8) prescaler y(8) timer 1( 8 ) timer 2( 8 ) sub-clock input x out x cin x cout sub-clock output watchdog timer reset p2(8) p3(8) i/o port p2 i/o port p3 p4(8) i/o port p4 i c int 3 1 3 5 2 4 36 38 35 37 39 6810 14 791113 p1(8) i/o port p1 19 21 23 25 20 22 24 26 p0(8) i/o port p0 27 28 29 30 31 32 33 34 pwm (8) 2 x cin x cout 48 47 46 40 41 42 si/o2(8)
4/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge v cc , v ss pin description functions name pin ?apply voltage of 2.7 v C 5.5 v to vcc, and 0 v to vss. ?this pin controls the operation mode of the chip. ?normally connected to v ss . ?reset input pin for active l. ?input and output pins for the clock generating circuit. ?connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ?when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. power source table 1 pin description function except a port function clock input clock output i/o port p0 cnv ss input cnv ss reset reset input x in x out p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 ? sub-clock generating circuit i/o pins (connect a resonator) i/o port p1 i/o port p2 p0 4 Cp0 7 i/o port p3 i/o port p4 ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?p2 2 to p2 5 can be switched between cmos compat- ible input level or smbus input level in the i 2 c-bus interface function. ?p2 0 , p2 1 , p2 4 to p2 7 : cmos3-state output structure. ?p2 4 , p2 5 : n-channel open-drain structure in the i 2 c- bus interface function. ?p2 2 , p2 3 : n-channel open-drain structure. ?8-bit cmos i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ?8-bit cmos i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ? i 2 c-bus interface function pins ? i 2 c-bus interface function pin/ serial i/o1 function pins ? serial i/o1 function pin ? serial i/o1 function pin/ timer x function pin ? a-d converter input pin ? timer y function pin ? interrupt input pins ? interrupt input pins ? s cmp2 output pin ? interrupt input pin ? pwm output pin p1 0 Cp1 7 p2 0 /x cout p2 1 /x cin p2 4 /sda 2 /rxd p2 5 /scl 2 /txd p2 2 /sda 1 p2 3 /scl 1 p2 6 /s clk ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?p1 0 to p1 7 (8 bits) are enabled to output large current for led drive. ? serial i/o2 function pins p2 7 /cntr 0 / s rdy1 p3 0 /an 0 C p3 7 /an 7 p4 0 /cntr 1 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm p4 5 Cp4 7 p4 1 /int 0 p4 2 /int 1
5/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge functional description central processing unit (cpu) the m37516m6-xxxhp uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and ma- chine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 . fig. 3 structure of cpu mode register cpu mode register ( cpum : address 003b 16 ) b7 b0 stack page selection bit 0 : 0 page 1 : 1 page not used (return ??when read) (do not write ??to this bit.) processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin ? cout oscillating function main clock (x in ? out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bits b7 b6 0 0 : f = f(x in )/2 (high-speed mode) 0 1 : f = f(x in )/8 (middle-speed mode) 1 0 : f = f(x cin )/2 (low-speed mode) 1 1 : not available
6/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 4 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 023f 16 a000 16 a080 16 ram 640 bytes rom 24 kbytes 0440 16 sfr area not used interrupt vector area reserved rom area (128 bytes) zero page special page reserved rom area reserved area
7/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 5 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) transmit/receive buffer register (tb/rb) serial i/o1 status register (siosts) serial i/o1 control register (siocon) uart control register (uartcon) baud rate generator (brg) interrupt control register 2 (icon2) a-d conversion low-order register (adl) prescaler y (prey) timer y (ty) a-d control register (adcon) a-d conversion high-order register (adh) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) prescaler 12 (pre12) timer 2 (t2) prescaler x (prex) timer x (tx) timer 1 (t1) timer xy mode register (tm) i 2 c data shift register (s0) i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) misrg watchdog timer control register (wdtcon) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) timer count source selection register (tcss) serial i/o2 control register1 (sio2con1) serial i/o2 control register2 (sio2con2) serial i/o2 register (sio2)
8/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge pin name input/output i/o structure non-port function ref.no. (1) (2) (3) (4) table 2 i/o port function related sfrs i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. port p0 p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 p0 4 Cp0 7 port p1 port p3 input/output, individual bits cmos compatible input level cmos 3-state output sub-clock generating circuit cpu mode register (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) p2 2 /sda 1 p2 3 /scl 1 port p2 p2 4 /sda 2 /rxd p2 5 /scl 2 /txd p2 6 /s clk p2 7 /cntr 0 /s rdy1 port p4 cmos compatible input level cmos/smbus input level (when selecting i 2 c-bus interface function) n-channel open-drain output cmos compatible input level cmos/smbus input level (when selecting i 2 c-bus interface function) cmos 3-state output n-channel open-drain output (when selecting i 2 c-bus interface function) cmos compatible input level cmos 3-state output i 2 c-bus interface func- tion i/o i 2 c-bus interface func- tion i/o serial i/o1 function i/o serial i/o1 function i/o serial i/o1 function i/o timer x function i/o a-d conversion input i 2 c control register i 2 c control register serial i/o1 control register serial i/o1 control register serial i/o1 control register timer xy mode register a-d control register timer xy mode register interrupt edge selection register interrupt edge selection register serial i/o2 control register interrupt edge selection register pwm control register p1 0 Cp1 7 p2 0 /x cout p2 1 /x cin p3 0 /an 0 p3 7 /an 7 p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm p4 5 p4 7 serial i/o2 function i/o serial i/o2 control register (16) (17) (18) (5) timer y function i/o external interrupt input external interrupt input s cmp2 output external interrupt input pwm output
9/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 6 port block diagram (1) serial i/o2 synchronous clock selection bit s rdy2 output enable bit (4) port p0 3 data bus direction register port latch serial i/o2 input (1) port p0 0 (2) port p0 1 p0 1 /s out2 p-channel output disable bit serial i/o2 transmit completion signal serial i/o2 port selection bit (3) port p0 2 serial i/o2 clock output serial i/o2 external clock input p0 2 /s clk2 p-channel output disable bit serial i/o2 port selection bit direction register port latch data bus serial i/o2 output direction register port latch data bus data bus port latch direction register serial i/o2 ready output (5) port p0 4 -p0 7 , p1, p4 5 -p4 7 direction register data bus port latch (7) port p2 1 port x c switch bit data bus port latch direction register sub-clock generating circuit input (6) port p2 0 port x c switch bit oscillator port p2 1 data bus port latch direction register port x c switch bit (8) port p2 2 data bus port latch direction register sda output i c-bus interface enable bit sda/scl pin selection bit sda input 2
10/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 7 port block diagram (2) (9) port p2 3 data bus port latch direction register scl output i 2 c-bus interface enable bit sda/scl pin selection bit scl input (10) port p2 4 data bus port latch direction register sda output serial i/o1 enable bit receive enable bit i 2 c-bus interface enable bit sda/scl pin selection bit sda input serial i/o1 input (12) port p2 6 data bus port latch direction register serial i/o1 clock output serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 clock selection bit external clock input (11) port p2 5 data bus port latch direction register scl output i 2 c bus interface enable bit sda/scl pin selection bit serial i/o1 enable bit transmit enable bit scl input serial i/o1 output p-channel output disable bit (14) port p3 0 Cp3 7 direction register data bus port latch (15) port p4 0 cntr 1 interrupt input data bus port latch direction register (13) port p2 7 data bus port latch direction register timer output serial i/o1 enable bit s rdy1 output enable bit serial i/o1 mode selection bit cntr 0 interrupt input serial ready output a-d converter input analog input pin selection bit (16) port p4 1 , p4 2 direction register data bus port latch interrupt input pulse output mode timer output pulse output mode pulse output mode
11/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 8 port block diagram (3) (18) port p4 4 pwm output data bus port latch direction register pwm output enable bit (17) port p4 3 interrupt input data bus port latch direction register serial i/o2 i/o comparison signal output serial i/o2 i/o comparison signal control bit interrupt input
12/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge interrupts interrupts occur by 17 sources among 17 sources: seven external, nine internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. n notes when the active edge of an external interrupt (int 0 Cint 3 , scl/ sda, cntr 0 , cntr 1 ) is set, the corresponding interrupt request bit may also be set. therefore, take the following sequence: 1. disable the interrupt 2. change the interrupt edge selection register (scl/sda interrupt pin polarity selection bit for scl/sda; the timer xy mode register for cntr 0 and cntr 1 ) 3. clear the interrupt request bit to 0 4. accept the interrupt.
13/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge interrupt request generating conditions remarks interrupt source low fffc 16 high fffd 16 priority 1 table 3 interrupt vector addresses and priority notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 scl, sda int 1 int 2 int 3 / serial i/o2 i 2 c timer x timer y timer 1 timer 2 serial i/o1 reception serial i/o1 transmission cntr 0 cntr 1 a-d converter brk instruction at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at completion of data transfer at completion of serial i/o1 data reception at completion of serial i/o1 transfer shift or when transmis- sion buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected valid when serial i/o is selected external interrupt (active edge selectable) stp release timer underflow external interrupt (active edge selectable) at detection of either rising or falling edge of s cl or s da input at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of a-d conversion at brk instruction execution external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdc 16 ffdd 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
14/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 9 interrupt control fig. 10 structure of interrupt-related registers (1) interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 active edge selection bit int 1 active edge selection bit int 2 active edge selection bit int 3 active edge selection bit serial i/o2 / int 3 interrupt source bit not used (returns 0 when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit scl/sda interrupt request bit int 1 interrupt request bit int 2 interrupt request bit int 3 / serial i/o2 interrupt request bit i 2 c interrupt request bit timer x interrupt request bit timer y interrupt request bit interrupt control register 1 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 timer 1 interrupt request bit timer 2 interrupt request bit serial i/o1 reception interrupt request bit serial i/o1 transmit interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit ad converter interrupt request bit not used (returns 0 when read) (ireq2 : address 003d 16 ) interrupt control register 2 timer 1 interrupt enable bit timer 2 interrupt enable bit serial i/o1 reception interrupt enable bit serial i/o1 transmit interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit ad converter interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : no interrupt request issued 1 : interrupt request issued 0 : interrupts disabled 1 : interrupts enabled 0 : falling edge active 1 : rising edge active 0 : int 3 interrupt selected 1 : serial i/o2 interrupt selected int 0 interrupt enable bit scl/sda interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit int 3 / serial i/o2 interrupt enable bit i 2 c interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit
15/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge timers the m37516m6-xxxhp has four timers: timer x, timer y, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are count down. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1. timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. the out- put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. timer x and timer y timer x and timer y can each select in one of four operating modes by setting the timer xy mode register. (1) timer mode the timer counts the count source selected by timer count source selection bit. (2) pulse output mode the timer counts the count source selected by timer count source selection bit. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge selection bit is 0, output begins at h. if it is 1, output starts at l. when using a timer in this mode, set the corresponding port p2 7 ( or port p4 0 ) direction register to out- put mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 or cntr 1 pin. when the cntr 0 (or cntr 1 ) active edge selection bit is 0, the rising edge of the cntr 0 (or cntr 1 ) pin is counted. when the cntr 0 (or cntr 1 ) active edge selection bit is 1, the falling edge of the cntr 0 (or cntr 1 ) pin is counted. (4) pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0, the timer counts the selected signals by the count source selection bit while the cntr 0 (or cntr 1 ) pin is at h. if the cntr 0 (or cntr 1 ) ac- tive edge selection bit is 1, the timer counts it while the cntr 0 (or cntr 1 ) pin is at l. the count can be stopped by setting 1 to the timer x (or timer y) count stop bit in any mode. the corresponding interrupt request bit is set each time a timer underflows. fig. 11 structure of timer xy mode register n note when switching the count source by the timer 12, x and y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer. fig. 12 structure of timer count source selection register timer x count stop bit 0: count start 1: count stop timer xy mode register (tm : address 0023 16 ) timer y operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b7 cntr 0 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b0 timer x operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode b1b0 b5b4 timer y count stop bit 0: count start 1: count stop timer count source selection register (tcss : address 0028 16 ) b7 b0 timer x count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer y count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer 12 count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x cin ) not used (returns 0 when read)
16/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 13 block diagram of timer x, timer y, timer 1, and timer 2 q q 1 0 p2 7 /cntr 0 q q p4 0 /cntr 1 0 1 r r 1 0 0 1 t t prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) to timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode to cntr 0 interrupt request bit pulse output mode port p2 7 latch port p2 7 direction register cntr 0 active edge selection bit timer x latch write pulse pulse output mode timer mode pulse output mode prescaler y latch (8) prescaler y (8) timer y latch (8) timer y (8) to timer y interrupt request bit toggle flip-flop timer y count stop bit to cntr 1 interrupt request bit pulse output mode port p4 0 latch port p4 0 direction register cntr 1 active edge selection bit timer y latch write pulse pulse output mode timer mode pulse output mode data bus data bus prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) data bus timer 2 latch (8) timer 2 (8) to timer 2 interrupt request bit to timer 1 interrupt request bit cntr 0 active edge selection bit cntr 1 active edge selection bit pulse width measure- ment mode event counter mode f(x cin ) timer 12 count source selection bit f(x in )/16 f(x in )/2 timer y count source selection bit f(x in )/16 f(x in )/2 timer x count source selection bit f(x in )/16
17/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. fig. 14 block diagram of clock synchronous serial i/o1 fig. 15 operation of clock synchronous serial i/o1 function 1/4 1/4 f/f p2 6 /s clk serial i/o1 status register serial i/o1 control register p2 7 /s rdy1 p2 4 /r x d p2 5 /t x d x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy1
18/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit (b6) of the serial i/o1 control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig.16 block diagram of uart serial i/o1 x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p2 6 /s clk1 serial i/o1 status register p2 4 /r x d p2 5 /t x d
19/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 17 operation of uart serial i/o1 function [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. [serial i/o1 status register (siosts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. serial i/o1 control register (siocon)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p2 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. n note when using the serial i/o1, clear the i 2 c-bus interface enable bit to 0 or the scl/sda pin selection bit to 0. tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?,? can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes serial output t x d serial input r x d receive buffer read signal
20/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 18 structure of serial i/o1 control registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns 1 when read) serial i/o1 status register serial i/o1 control register b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o1 is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o1 is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p2 7 pin operates as ordinary i/o pin 1: p2 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p2 4 to p2 7 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p2 4 to p2 7 operate as serial i/o1 pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p2 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 (siosts : address 0019 16 ) (siocon : address 001a 16 ) (uartcon : address 001b 16 )
21/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge l serial i/o2 the serial i/o2 can be operated only as the clock synchronous type. as a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial i/o2 synchronous clock selection bit (b6) of serial i/o2 control register 1. the internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selec- tion bit (b2, b1, b0) of serial i/o2 control register 1. regarding s out2 and s clk2 being output pins, either cmos output format or n-channel open-drain output format can be selected by the p0 1 /s out2 , p0 2 /s clk2 p-channel output disable bit (b7) of serial i/o2 control register 1. when the internal clock has been selected, a transfer starts by a write signal to the serial i/o2 register (address 0017 16 ). after comple- tion of data transfer, the level of the s out2 pin goes to high imped- ance automatically but bit 7 of the serial i/o2 control register 2 is not set to "1" automatically. when the external clock has been selected, the contents of the serial i/o2 register is continuously sifted while transfer clocks are input. accordingly, control the clock externally. note that the s out2 pin does not go to high impedance after completion of data trans- fer. to cause the s out2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial i/o2 control register 2 to "1" when s clk2 is "h" after completion of data transfer. after the next data transfer is started (the transfer clock falls), bit 7 of the serial i/o2 control register 2 is set to "0" and the s out2 pin is put into the active state. regardless of the internal clock to external clock, the interrupt re- quest bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. in case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial i/o2 register becomes a fractional number of bits close to msb if the transfer direction selection bit of serial i/o2 control register 1 is lsb first, or a fractional number of bits close to lsb if the said bit is msb first. for the remaining bits, the previously re- ceived data is shifted. at transmit operation using the clock synchronous serial i/o, the s cmp2 signal can be output by comparing the state of the transmit pin s out2 with the state of the receive pin s in2 in synchronization with a rise of the transfer clock. if the output level of the s out2 pin is equal to the input level to the s in2 pin, "l" is output from the s cmp2 pin. if not, "h" is output. at this time, an int 2 interrupt request can also be generated. select a valid edge by bit 2 of the interrupt edge selection register (address 003a 16 ). [serial i/o2 control registers 1, 2] sio2con1 / sio2con2 the serial i/o2 control registers 1 and 2 are containing various se- lection bits for serial i/o2 control as shown in figure 19. fig. 19 structure of serial i/o2 control registers 1, 2 serial i/o2 control register 1 (sio2con1 : address 0015 16 ) serial i/o2 control register 2 (sio2con2 : address 0016 16 ) b7 b7 b0 optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit not used ( returns "0" when read) serial i/o2 i/o comparison signal control bit 0: p4 3 i/o 1: s cmp2 output s out2 pin control bit (p0 1 ) 0: output active 1: output high-impedance internal synchronous clock selection bit b2 b1 b0 0 0 0: f(x in )/8 (f(x cin )/8 in low-speed mode) 0 0 1: f(x in )/16 (f(x cin )/16 in low-speed mode) 0 1 0: f(x in )/32 (f(x cin )/32 in low-speed mode) 0 1 1: f(x in )/64 (f(x cin )/64 in low-speed mode) 1 1 0: f(x in )/128 f(x cin )/128 in low-speed mode) 1 1 1: f(x in )/256 (f(x cin )/256 in low-speed mode) serial i/o2 port selection bit 0: i/o port 1: s out2 ,s clk2 output pin s rdy2 output enable bit 0: p0 3 pin is norma l i/o pin 1: p0 3 pin is s rdy2 output pin transfer direction selection bit 0: lsb first 1: msb first serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock p0 1 /s out2 , p0 2 /s clk2 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode ) b0
22/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 20 block diagram of serial i/o2 fig. 21 timing chart of serial i/o2 x in "1" "0" "0" "1" "0" "1" s rdy2 s clk2 "0" "1" 1/8 1/16 1/32 1/64 1/128 1/256 "1" "0" x cin "10" "00" "01" data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o2 register (8) synchronous circuit serial i/o2 port selection bit serial i/o2 synchronous clock selection bit s rdy2 output enable bit external clock internal synchronous clock selection bit divider optional transfer bits (3) p0 2 /s clk2 p0 1 /s out2 p0 0 /s in2 p0 2 latch p0 1 latch p0 3 latch p0 3 /s rdy2 p4 3 /s cmp2 /int 2 serial i/o2 i/o comparison signal control bit p4 3 latch q d main clock division ratio selection bits (note) note: either hi g h-speed , middle-speed or low-speed mode is selected b y bits 6 and 7 of cpu mode re g ister. d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) serial i/o2 output s out2 serial i/o2 input s in2 receive enable signal s rdy2 write-in signal to serial i/o2 register (note 2) serial i/o2 interrupt request bit set . 1: when the internal clock is selected as a transfer clock, the f(x in ) clock division (f(x cin ) in low-speed mode) can be selected by setting bits 0 to 2 of serial i/o2 control register 1. 2: when the internal clock is selected as a transfer clock, the s cout2 pin has high impedance after transfer completion. notes
23/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 22 s cmp2 output operation s clk2 s in2 s out2 s cmp2 judgement of i/o data comparison
24/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at = 4 mhz) table 4 multi-master i 2 c-bus interface functions item format communication mode system clock = f(x in )/2 (high-speed mode) = f(x in )/8 (middle-speed mode) multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchro- nous functions, is useful for the multi-master serial communications. figure 23 shows a block diagram of the multi-master i 2 c-bus in- terface and table 4 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to . note: mitsubishi electric corporation assumes no responsibility for in- fringement of any third-partys rights or originating in the use of the connection control function between the i 2 c-bus interface and the ports scl 1 , scl 2 , sda 1 and sda 2 with the bit 6 of i 2 c control regis- ter (002e 16 ). fig. 23 block diagram of multi-master i 2 c-bus interface ] : purchase of mitsubishi electric corporations i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. scl clock frequency i 2 c address register b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb noise elimination circuit address comparator b7 i 2 c data shift register b0 data control circuit system clock (f) interrupt generating circuit interrupt request signal (iicirq) b7 ms t trx bb pin al aas ad0 lrb b0 s1 b7 b0 tiss 10bit sad als bc2 bc1 bc0 s1d bit counter bb circuit clock control circuit noise elimination circuit b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 s2 s0d al circuit es0 sis i 2 c start/stop condition control register sip ssc4ssc3 ssc2 ssc1 ssc0 i 2 c clock control register i 2 c status register s2d tsel i 2 c clock control register s1d i c control register 2 serial data (s da ) serial clock (s cl )
25/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge [i 2 c data shift register (s0)] 002b 16 the i 2 c data shift register (s0 : address 002b 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 machine cycles are required from the rising of the scl clock until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit : bit 3 of address 002e 16 ) of the i 2 c control register is 1. the bit counter is reset by a write in- struction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (address 002d 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled re- gardless of the es0 bit value. [i 2 c address register (s0d)] 002c 16 the i 2 c address register (address 002c 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the start condition is de- tected. ?bit 0: read/write bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rwb) of the i 2 c address reg- ister. the rwb bit is cleared to 0 automatically when the stop condi- tion is detected. ?bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address fig. 24 structure of i 2 c address register sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb slave address i 2 c address register (s0d: address 002c 16 ) read/write bit b7 b0
26/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge table 5 set values of i 2 c clock control register and scl frequency fig. 25 structure of i 2 c clock control register scl frequency (at f = 4 mhz, unit : khz) setting value of ccr4Cccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 setting disabled setting disabled setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (note 3) 166 C (note 2) C (note 2) [i 2 c clock control register (s2)] 002f 16 the i 2 c clock control register (address 002f 16 ) is used to set ack control, scl mode and scl frequency. ?bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to table 5. ?bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the standard clock mode is selected. when the bit is set to 1, the high-speed clock mode is selected. when connecting the bus of the high-speed mode i 2 c bus stan- dard (maximum 400 kbits/s), use 8 mhz or more oscillation frequency f(x in ) and 2 division clock. ?bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is selected and sda goes to l at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is selected. the sda is held in the h status at the occurrence of an ack clock. however, when the slave address agree with the address data in the reception of address data at ack bit = 0, the sda is auto- matically made l (ack is returned). if there is a disagreement between the slave address and the address data, the sda is auto- matically made h (ack is not returned). ] ack clock: clock for acknowledgment ?bit 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. when this bit is set to 0, the no ack clock mode is selected. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (makes sda h) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transfer. if data is written during transfer, the i 2 c clock generator is reset, so that data cannot be transferred normally. 500/ccr value (note 3) 1000/ccr value (note 3) 17.2 16.6 16.1 notes 1: duty of scl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at f = 4 mhz). h duration of the clock fluctuates from C4 to +2 machine cycles in the standard clock mode, and fluctuates from C2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduction. these are value when scl clock synchronization by the syn- chronous function is not performed. ccr value is the decimal notation value of the scl frequency control bits ccr4 to ccr0. 2: each value of scl frequency exceeds the limit at f = 4 mhz or more. when using these setting value, use f of 4 mhz or less. 3: the data formula of scl frequency is described below: f /(8 5 ccr value) standard clock mode f /(4 5 ccr value) high-speed clock mode (ccr value 1 5) f /(2 5 ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of f frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the scl frequency by setting the scl frequency control bits ccr4 to ccr0. ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i 2 c clock control register (s2 : address 002f 16 ) b7 b0 scl frequency control bits refer to table 5. scl mode specification bit 0 : standard clock mode 1 : high-speed clock mode ack bit 0 : ack is returned. 1 : ack is not returned. ack clock bit 0 : no ack clock 1 : ack clock
27/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 27 structure of i 2 c control register [i 2 c control register (s1d)] 002e 16 the i 2 c control register (address 002e 16 ) controls data communi- cation format. ?bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signal occurs immediately after the number of count specified with these bits (ack clock is added to the number of count when ack clock is selected by ack clock bit (bit 7 of address 002f 16 )) have been transferred, and bc0 to bc2 are returned to 000 2 . also when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. ?bit 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c-bus interface. when this bit is set to 0, the use disable status is provided, so that the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when es0 = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (which are bits of the i 2 c status register at address 002d 16 ). ? writing data to the i 2 c data shift register (address 002b 16 ) is dis- abled. ?bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to i 2 c status register, bit 1) is re- ceived, transfer processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recognized. ?bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address regis- ter (address 002c 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, and all the bits of the i 2 c address register are compared with address data. ?bit 6: sda/scl pin selection bit this bit selects the input/output pins of scl and sda of the multi- master i 2 c-bus interface. ?bit 7: i 2 c-bus interface pin input level selection bit this bit selects the input level of the scl and sda pins of the multi-master i 2 c-bus interface. fig. 26 sda/scl pin selection bit b7 tiss tsel 10 bit sad als es0 bc2 bc1 bc0 b0 sda/scl pin selection bit 0 : connect to ports p2 2 , p2 3 1 : connect to ports p2 4 , p2 5 i 2 c control register (s1d : address 002e 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 00 0: 8 00 1: 7 01 0: 6 01 1: 5 10 0: 4 10 1: 3 11 0: 2 11 1: 1 i 2 c-bus interface enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format i 2 c-bus interface pin input level selection bit 0 : cmos input 1 : smbus input scl sda multi-master i 2 c-bus interface tsel scl 1 /p2 3 scl 2 /txd/p2 5 sda 1 /p2 2 sda 2 /rxd/p2 4 tsel tsel tsel
28/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge ?bit 4: scl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit changes from 1 to 0. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 29 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions: ? executing a write instruction to the i 2 c data shift register (ad- dress 002b 16 ). (this is the only condition which the prohibition of the internal clock is released and data can be communicated ex- cept for the start condition detection.) ? when the es0 bit is 0 ? at reset ? when writing 1 to the pin bit by software the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately af- ter completion of slave address agreement or general call address reception ? in the slave reception mode, with als = 1 and immediately af- ter completion of address data reception ?bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the scl, sda pins input signal regardless of master/slave. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detecting is set by the start/stop condition setting bits (ssc4Cssc0) of the i 2 c start/stop condition control register (address 0030 16 ). when the es0 bit of the i 2 c control register (address 002e 16 ) is 0 or reset, the bb flag is set to 0. for the writing function to the bb flag, refer to the sections start condition generating method and stop condition gen- erating method described later. [i 2 c status register (s1)] 002d 16 the i 2 c status register (address 002d 16 ) controls the i 2 c-bus in- terface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set 0000 2 to the low-order 4 bits, because these bits become the reserved bits at writing. ?bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ). ?bit 1: general call detecting flag (ad0) when the als bit is 0, this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives con- trol data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition, or reset. ] general call: the master transmits the general call address 00 16 to all slaves. ?bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is 0. ? in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions: ? the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-or- der 7 bits of the i 2 c address register (address 002c 16 ). ? a general call is received. ? in the slave receive mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition: ? when the address data is compared with the i 2 c address reg- ister (8 bits consisting of slave address and rwb bit), the first bytes agree. ? this bit is set to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ) when es0 is set to 1 or reset. ?bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitration was lost is completed, the mst bit is set to 0. the arbitration lost can be detected only in the master transmission mode. when ar- bitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ] arbitration lost : the status in which communication as a master is dis- abled.
29/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 29 interrupt request signal generating timing fig. 28 structure of i 2 c status register ?bit 6: communication mode specification bit (transfer direc- tion specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a transmitting device is received. when the bit is 1, the transmis- sion mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the scl. this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to 1 by hardware when all the following conditions are satisfied: ? when als is 0 ? in the slave reception mode or the slave transmission mode ? when the r/w bit reception is 1 this bit is set to 0 in one of the following conditions: ? when arbitration lost is detected. ? when a stop condition is detected. ? when writing 1 to this bit by software is invalid by the start condition duplication preventing function (note) . ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset ?bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communi- cation are generated on the scl. this bit is set to 0 in one of the following conditions. ? immediately after completion of 1-byte data transfer when arbi- tration lost is detected ? when a stop condition is detected. ? writing 1 to this bit by software is invalid by the start condi- tion duplication preventing function (note) . ? at reset note: start condition duplication preventing function the mst, trx, and bb bits is set to 1 at the same time after con- firming that the bb flag is 0 in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to 1 immediately after the con- tents of the bb flag is confirmed, the start condition duplication preventing function makes the writing to the mst and trx bits in- valid. the duplication preventing function becomes valid from the rising of the bb flag to reception completion of slave address. scl pin iicirq b7 mst b0 i 2 c status register (s1 : address 002d 16 ) last receive bit (note) 0 : last bit = ?? 1 : last bit = ?? general call detecting flag (note) 0 : no general call detected 1 : general call detected slave address comparison flag (note) 0 : address disagreement 1 : address agreement arbitration lost detecting flag (note) 0 : not detected 1 : detected scl pin low hold bit 0 : scl pin low hold 1 : scl pin low release bus busy flag 0 : bus free 1 : bus busy communication mode specification bits 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode trx bb pin al aas ad0 lrb note: these bits and flags can be read out, but cannot be written. write ??to these bits at writing.
30/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 32 start condition detecting timing diagram start/stop condition detecting operation the start/stop condition detection operations are shown in figures 32, 33, and table 8. the start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the scl and sda pins satisfy three conditions: scl re- lease time, setup time, and hold time (see table 8). the bb flag is set to 1 by detecting the start condition and is reset to 0 by detecting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock mode. refer to table 8, the bb flag set/ reset time. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq occurs to the cpu. start condition generating method when writing 1 to the mst, trx, and bb bits of the i 2 c status register (address 002d 16 ) at the same time after writing the slave address to the i 2 c data shift register (address 002b 16 ) with the condition in which the es0 bit of the i 2 c control register (address 002e 16 ) is 1 and the bb flag is 0, a start condition occurs. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 30, the start condition generating timing diagram, and table 6, the start condition generating timing table. stop condition generating method when the es0 bit of the i 2 c control register (address 002e 16 ) is 1, write 1 to the mst and trx bits, and write 0 to the bb bit of the i 2 c status register (address 002d 16 ) simultaneously. then a stop condition occurs. the stop condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 31, the stop condition generating timing diagram, and table 7, the stop condition generating timing table. fig. 30 start condition generating timing diagram fig. 31 stop condition generating timing diagram table 7 stop condition generating timing table item setup time hold time standard clock mode 5.0 us (20 cycles) 4.5 us (18 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 3.0 us (12 cycles) 2.5 us (10 cycles) table 6 start condition generating timing table item setup time hold time standard clock mode 5.0 us (20 cycles) 5.0 us (20 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 2.5 us (10 cycles) 2.5 us (10 cycles) table 8 start condition/stop condition detecting conditions note: unit : cycle number of system clock ssc value is the decimal notation value of the start/stop condi- tion set bits ssc4 to ssc0. do not set 0 or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/ stop condition control register is set to 18 16 at = 4 mhz. fig. 33 stop condition detecting timing diagram scl release time standard clock mode high-speed clock mode 4 cycles (1.0 us) 2 cycles (1.0 us) 2 cycles (0.5 us) 3.5 cycles (0.875 us) scc value + 1 2 scc value + 1 2 scc value C1 2 setup time hold time bb flag set/ reset time scc value + 1 cycle (6.25 us) cycle < 4.0 us (3.125 us) cycle < 4.0 us (3.125 us) + 2 cycles (3.375 us) i 2 c status register write signal aaa aaa hold time setup time scl sda aaa aaa hold time setup time scl sda bb fla g aaa aaa scl release time bb flag reset time i 2 c status register write signal aaa aaa hold time setup time scl sda aaa hold time setup time scl sda bb flag aaaa scl release time bb flag set time
31/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge [i 2 c start/stop condition control register (s2d)] 0030 16 the i 2 c start/stop condition control register (address 0030 16 ) controls start/stop condition detection. ?bits 0 to 4: start/stop condition set bit (ssc4Cssc0) scl release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/stop condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 8. do not set 00000 2 or an odd number to the start/stop condi- tion set bit (ssc4 to ssc0). refer to table 9, the recommended set value to start/stop condition set bits (ssc4Cssc0) for each oscillation frequency. ?bit 5: scl/sda interrupt pin polarity selection bit (sip) an interrupt can occur when detecting the falling or rising edge of the scl or sda pin. this bit selects the polarity of the scl or sda pin interrupt pin. ?bit 6: scl/sda interrupt pin selection bit (sis) this bit selects the pin of which interrupt becomes valid between the scl pin and the sda pin. note: when changing the setting of the scl/sda interrupt pin polarity se- lection bit, the scl/sda interrupt pin selection bit, or the i 2 c-bus interface enable bit es0, the scl/sda interrupt request bit may be set. when selecting the scl/sda interrupt source, disable the inter- rupt before the scl/sda interrupt pin polarity selection bit, the scl/ sda interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to 0 after setting these bits, and enable the interrupt. address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats are described below. ? 7-bit addressing format to adapt the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, address com- parison of the rwb bit of the i 2 c address register (address 002c 16 ) is not performed. for the data transmission format when the 7-bit addressing format is selected, refer to figure 35, (1) and (2). ? 10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 1. an address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, an address comparison between the rwb bit of the i 2 c address register (address 002c 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is pro- cessed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (address 002d 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 002b 16 ), perform an address com- parison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rwb bit of the i 2 c address register (address 002c 16 ) to 1 by software. this processing can make the 7-bit slave address and r/w data agree, which are re- ceived after a restart condition is detected, with the value of the i 2 c address register (address 002c 16 ). for the data trans- mission format when the 10-bit addressing format is selected, refer to figure 35, (3) and (4).
32/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge start/stop condition control register oscillation frequency f(x in ) (mhz) fig. 35 address data communication format fig. 34 structure of i 2 c start/stop condition control register note: do not set 00000 2 or an odd number to the start/stop condition set bit (ssc4 to ssc0). table 9 recommended set value to start/stop condition set bits (ssc4Cssc0) for each oscillation frequency main clock divide ratio system clock f (mhz) scl release time ( m s) setup time ( m s) hold time ( m s) 8 8 4 2 2 8 2 2 xxx11010 xxx11000 xxx00100 xxx01100 xxx01010 xxx00100 3.375 m s (13.5 cycles) 3.125 m s (12.5 cycles) 2.5 m s (2.5 cycles) 3.25 m s (6.5 cycles) 2.75 m s (5.5 cycles) 2.5 m s (2.5 cycles) 6.75 m s (27 cycles) 6.25 m s (25 cycles) 5.0 m s (5 cycles) 6.5 m s (13 cycles) 5.5 m s (11 cycles) 5.0 m s (5 cycles) 3.375 m s (13.5 cycles) 3.125 m s (12.5 cycles) 2.5 m s (2.5 cycles) 3.25 m s (6.5 cycles) 2.75 m s (5.5 cycles) 2.5 m s (2.5 cycles) 4 1 2 1 s slave address r/w a data a/a p a data 7 bits ? 1 to 8 bits 1 to 8 bits (1) a master-transmitter transnmits data to a slave-receiver s slave address r/w a data a p a data 7 bits ? 1 to 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitter 7 bits ? 8 bits (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address 1 to 8 bits 1 to 8 bits s r/w a slave address 1st 7 bits slave address 2nd bytes a a data data p a/a 7 bits ? 8 bits (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition a : ack bit sr : restart condition p : stop condition r/w : read/write bit 7 bits ? 1 to 8 bits 1 to 8 bits s r/w a slave address 1st 7 bits slave address 2nd bytes a sr slave address 1st 7 bits r/w a data data p a : master to slave : slave to master a b7 b0 i 2 c start/stop condition control register start/stop condition set bit scl/sda interrupt pin polarity selection bit 0 : falling edge active 1 : rising edge active scl/sda interrupt pin selection bit 0 : sda valid 1 : scl valid reserved do not write ??to this bit. sis sip ssc4 ssc3 ssc2 ssc1 ssc0 (s2d : address 0030 16 )
33/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. (1) set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 into the rwb bit. (2) set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 002f 16 ). (3) set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. (4) set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). (5) confirm the bus free condition by the bb flag of the i 2 c status register (address 002d 16 ). (6) set the address data of the destination of transmission in the high-order 7 bits of the i 2 c data shift register (address 002b 16 ) and set 0 in the least significant bit. (7) set f0 16 in the i 2 c status register (address 002d 16 ) to gener- ate a start condition. at this time, an scl for 1 byte and an ack clock automatically occur. (8) set transmit data in the i 2 c data shift register (address 002b 16 ). at this time, an scl and an ack clock automatically occur. (9) when transmitting control data of more than 1 byte, repeat step (8). (10) set d0 16 in the i 2 c status register (address 002d 16 ) to gen- erate a stop condition if ack is not returned from slave reception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. (1) set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 in the rwb bit. (2) set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 002f 16 ). (3) set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. (4) set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). (5) when a start condition is received, an address comparison is performed. (6) ?when all transmitted addresses are 0 (general call): ad0 of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. ? when the transmitted addresses agree with the address set in (1): ass of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. ? in the cases other than the above ad0 and aas of the i 2 c sta- tus register (address 002d 16 ) are set to 0 and no interrupt request signal occurs. (7) set dummy data in the i 2 c data shift register (address 002b 16 ). (8) when receiving control data of more than 1 byte, repeat step (7). (9) when a stop condition is detected, the communication ends.
34/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge (2) start condition generating procedure using multi-master 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 5. : : lda (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) : : busbusy: cli (interrupt enabled) : : 2. use branch on bit set of bbs 5, $002d, C for the bb flag confirming and branch process. 3. use sta $2b, stx $2b or sty $2b of the zero page ad- dressing instruction for writing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of above 2 and the store instruc- tion of above 3 continuously shown the above procedure example. 5. disable interrupts during the following three process steps: ? bb flag confirming ? writing of slave address value ? trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 4.) execute the following procedure when the pin bit is 0. : : ldm #$00, s1 (select slave receive mode) lda (t aking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 ( trigger of restart condition generating ) cli (interrupt enabled) : : 2. select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the sda pin is released. 3. the scl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: ? writing of slave address value ? trigger of restart condition generating (4) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simulta- neously. it is because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to 0 from 1 simultaneously when the pin bit is 1. it is because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c sta- tus register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. n precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 c data shift register (s0: address 002b 16 ) when executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended. ?i 2 c address register (s0d: address 002c 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the stop condition, data may become a value not intended. it is because h/w changes the read/write bit (rwb) at the above timing. ?i 2 c status register (s1: address 002d 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by h/w. ?i 2 c control register (s1d: address 002e 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the start condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter (bc0-bc2) at the above timing. ?i 2 c clock control register (s2: address 002f 16 ) the read-modify-write instruction can be executed for this regis- ter. ?i 2 c start/stop condition control register (s2d: address 0030 16 ) the read-modify-write instruction can be executed for this regis- ter.
35/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge pulse width modulation (pwm) the m37516m6-xxxhp has a pwm function with an 8-bit resolu- tion, based on a signal that is the clock input x in or that clock input divided by 2. data setting the pwm output pin also functions as port p4 4 . set the pwm pe- riod by the pwm prescaler, and set the h term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 5 (n+1) / f(x in ) = 31.875 5 (n+1) us (when f(x in ) = 8 mhz, count source is f(x in ) ) output pulse h term = pwm period 5 m / 255 = 0.125 5 (n+1) 5 m us (when f(x in ) = 8 mhz, count source is f(x in )) fig. 36 timing of pwm period fig. 37 block diagram of pwm function pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to 1, operation starts by initializing the pwm output circuit, and pulses are output starting at an h. if the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. 31.875 5 m 5 (n+1) 255 t = [31.875 5 (n+1)] pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 8 mhz, count source is f(x in )) us us data bus count source selection bit 0 1 pwm prescaler pre-latch pwm register pre-latch pwm prescaler latch pwm register latch transfer control circuit pwm register 1/2 x in port p4 4 latch pwm enable bit port p4 4 pwm prescaler
36/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 38 structure of pwm control register fig. 39 pwm output timing when pwm register or pwm prescaler is changed pwm control register (pwmcon : address 001d 16 ) pwm function enable bit count source selection bit not used (return 0 when read) b7 b0 0: pwm disabled 1: pwm enabled 0: f(x in ) 1: f(x in )/2 abc b t c t2 = pwm output pwm register write signal pwm prescaler write signal (changes ??term from ??to ??) (changes pwm period from ??to ?2?) when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change. t t t2 n note the pwm starts after the pwm enable bit is set to enable and "l" level is output from the pwm pin. the length of this "l" level output is as follows: sec (count source selection bit = 0, where n is the value set in the prescaler) sec (count source selection bit = 1, where n is the value set in the prescaler) n+1 2 ? f(x in ) n+1 f(x in )
37/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge a-d converter [a-d conversion registers (adl, adh)] 0035 16 , 0036 16 the a-d conversion registers are read-only registers that store the result of an a-d conversion. do not read these registers during an a-d conversion [ad control register (adcon)] 0034 16 the ad control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 4 indicates the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion and changes to 1 when an a-d conversion ends. writing 0 to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref into 1024 and outputs the divided voltages. channel selector the channel selector selects one of ports p3 0 /an 0 to p3 7 /an 7 and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage, and the result is stored in the a-d conversion registers. when an a-d conversion is completed, the control circuit sets the a-d conversion completion bit and the a-d interrupt request bit to 1. note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. when the a-d converter is operated at low-speed mode, f(x in ) and f(x cin ) do not have the lower limit of frequency, because of the a-d converter has a built-in self-oscillation circuit. fig. 40 structure of ad control register fig. 41 structure of a-d conversion registers fig. 42 block diagram of a-d converter ad control register (adcon : address 0034 16 ) analog input pin selection bits b2 b1 b0 0 0 0: p3 0 /an 0 0 0 1: p3 1 /an 1 0 1 0: p3 2 /an 2 0 1 1: p3 3 /an 3 1 0 0: p3 4 /an 4 1 0 1: p3 5 /an 5 1 1 0: p3 6 /an 6 1 1 1: p3 7 /an 7 not used (returns 0 when read) a-d conversion completion bit 0: conversion in progress 1: conversion completed not used (returns 0 when read) b7 b0 channel selector a-d control circuit a-d conversion low-order register resistor ladder v ref av ss comparator a-d interrupt request b7 b0 3 10 p3 0 /an 0 p3 1 /an 1 p3 2 /an 2 p3 3 /an 3 p3 4 /an 4 data bus ad control register a-d conversion high-order register (address 0034 16 ) (address 0036 16 ) (address 0035 16 ) p3 5 /an 5 p3 6 /an 6 p3 7 /an 7 10-bit reading (read address 0036 16 before 0035 16 ) (address 0036 16 ) (address 0035 16 ) 8-bit reading (read only address 0035 16 ) b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b9 b7 b0 note : the high-order 6 bits of address 0036 16 become ? at reading. b9 b8 b7 b6 b5 b4 b3 b2 b7 b0
38/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0039 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 0039 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watch- dog timer h count source selection bit are read. l initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0039 16 ), each watchdog timer h and l is set to ff 16 . fig. 44 structure of watchdog timer control register l watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0039 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0, the count source becomes the underflow signal of watchdog timer l. the detection time is set to 131.072 ms at f(x in ) = 8 mhz frequency and 32.768 s at f(x cin ) = 32 khz frequency. when this bit is set to 1, the count source becomes the signal divided by 16 for f(x in ) (or f(x cin )). the detection time in this case is set to 512 m s at f(x in ) = 8 mhz frequency and 128 ms at f(x cin ) = 32 khz frequency. this bit is cleared to 0 after resetting. l operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0039 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0, the stp instruction is enabled. when this bit is 1, the stp instruction is disabled, once the stp instruction is executed, an internal reset occurs. when this bit is set to 1, it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. fig. 43 block diagram of watchdog timer x in data bus x cin 10 00 01 main clock division ratio selection bits (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction ff 16 is set when watchdog timer control register is written to. b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 0039 16 ) b7
39/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge reset circuit to reset the microcomputer, reset pin must be held at an "l" level for 2 m s or more. then the reset pin is returned to an "h" level (the power source voltage must be between 2.7 v and 5.5 v, and the oscillation must be stable), reset is released. after the re- set is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.54 v for v cc of 2.7 v. fig. 46 reset sequence fig. 45 reset circuit example (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.7 v reset data f address sync x in : 8 to 13 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( f ) is f(x in ) = 2 f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. 3: all signals except x in and reset are internals. reset address from the vector table. notes reset out
40/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 47 internal status at reset port p0 direction register (p0d) port p1 direction register (p1d) port p2 direction register (p2d) port p3 direction register (p3d) port p4 direction register (p4d) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) pwm control register (pwmcon) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) timer count source select register i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) ad control register (adcon) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) processor status register program counter (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) note : x indicates not fixed . address register contents 0001 16 0003 16 0005 16 0007 16 0009 16 0019 16 001a 16 001b 16 001d 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 002c 16 002d 16 002e 16 002f 16 0030 16 0034 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pc h ) (pc l ) 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0001000x 000 10000000 11100000 1 01001 0 0 xx xx xx x 0001 0 000 00111111 0 fffd 16 contents fffc 16 contents xxxxx
41/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge clock generating circuit the m37516m6-xxxhp has two built-in oscillation circuits. an os- cillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in ac- cordance with the resonator manufacturers recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock f is the frequency of x in divided by 8. after re- set, this mode is selected. (2) high-speed mode the internal clock f is half the frequency of x in . (3) low-speed mode the internal clock f is half the frequency of x cin . n note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub-clock to stabilize, especially immediately af- ter power on and at returning from the stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3?f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0), set sufficient time for oscillation to stabilize. the sub-clock x cin -x cout oscillating circuit can not directly input clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. oscillation control (1) stop mode if the stp instruction is executed, the internal clock f stops at an h level, and x in and x cin oscillation stops. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. either x in or x cin divided by 16 is input to the prescaler 12 as count source. oscillator restarts when an external interrupt is re- ceived, but the internal clock f is not supplied to the cpu (remains at h) until timer 1 underflows. the internal clock f is supplied for the first time, when timer 1 underflows. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. when the oscillator is restarted by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not fig. 48 ceramic resonator circuit fig. 49 external clock input circuit x cin x cout x in x out c in c out c cin c cout rf rd x cin x cout x in x out c cin c cout rf rd open external oscillation circuit vcc vss be generated. (2) wait mode if the wit instruction is executed, the internal clock f stops at an h level, but the oscillator does not stop. the internal clock f re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to 1 before ex- ecuting of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock xin divided by 16. accordingly, set the timer 1 interrupt enable bit to 0 before executing the stp instruc- tion. n note when using the oscillation stabilizing time set after stp instruction released bit set to 1, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
42/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 51 system clock generating circuit block diagram (single-chip mode) misrg (misrg : address 0038 16 ) oscillation stabilizing time set after stp instruction released bit middle-speed mode automatic switch set bit middle-speed mode automatic switch wait time set bit middle-speed mode automatic switch start bit (depending on program) not used (return 0 when read) b7 b0 0: automatically set 01 16 to timer 1, ff 16 to prescaler 12 1: automatically set nothing 0: not set automatically 1: automatic switching enable 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles 0: invalid 1: automatic switch start fig. 50 structure of misrg middle-speed mode automatic switch set bit by setting the middle-speed mode automatic switch set bit to 1 while operating in the low-speed mode, x in oscillation automati- cally starts and the mode is automatically switched to the middle-speed mode when defecting a rising/falling edge of the scl or sda pin. the middle-speed automatic switch wait time set bit can select the switch timing from the low-speed to the middle- speed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5 machine cycles in the low-speed mode. select it according to os- cillation start characteristics of used x in oscillator. the middle-speed mode automatic switch start bit is used to auto- matically make to x in oscillation start and switch to the middle-speed mode by setting this bit to 1 while operating in the low-speed mode. wit instruction stp instruction timing f (internal clock) s r q stp instruction s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l 1/2 port x c switch bit ? ? low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note) note 1: any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port xc switch bit (b1) to ?? 2: when the oscillation stabilizing time set after stp instruction released bit is ?? main clock division ratio selection bits (note 1) ff 16 01 16 prescaler 12 timer 1 reset or stp instruction (note 2)
43/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 52 state transitions of system clock cm 4 : port xc switch bit 0 : i/o port function (stop oscillating) 1 : x cin -x cout oscillating function cm 5 : main clock (x in - x out ) stop bit 0 : oscillating 1 : stopped cm 7 , cm 6 : main clock division ratio selection bit b7 b6 0 0 : = f (x in )/2 ( high-speed mode) 0 1 : = f (x in )/8 (middle-speed mode) 1 0 : = f (x cin )/2 (low-speed mode) 1 1 : not available notes reset cm 4 ? ? cm 4 ? ? cm 6 ? ? cm 4 ? ? cm 6 ? ? cm 7 ? ? cm 4 ? ? cm 5 ? ? cm 6 ? ? cm 6 ? ? cpu mode register b7 b4 cm 7 ? ? cm 6 ? ? (cpum : address 003b 16 ) cm 7 =0 cm 6 =1 cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) middle-speed mode (f( )=1 mhz) cm 7 =0 cm 6 =1 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) middle-speed mode (f( )=1 mhz) cm 7 =0 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) high-speed mode (f( )=4 mhz) cm 7 =1 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( )=16 khz) cm 7 =1 cm 6 =0 cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) low-speed mode (f( )=16 khz) cm 7 =0 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) high-speed mode (f( )=4 mhz) 1 : switch the mode by the allows shown between the mode blocks. (do not switch between the modes directly without an allow.) 2 : the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mo de is ended. 3 : timer operates in the wait mode. 4 : when the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : when the stop mode is ended, the following is performed. (1) after the clock is restarted, a delay of approximately 16ms occurs in low-speed mode if timer 12 count source selec tion bit is "0". (2) after the clock is restarted, a delay of approximately 250ms occurs in low-speed mode if timer 12 count source selec tion bit is "1". 6 : wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/high-speed mode. 7 : the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock.
44/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. ? the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy1 signal, set the transmit enable bit, the receive enable bit, and the s rdy1 output enable bit to 1. serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high impedance after transmis- sion is completed. when an external clock is used as synchronous clock in serial i/ o1 or serial i/o2, write transmission data to the transmit buffer register or serial i/o2 register while the transfer clock is h. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency in high-speed mode. notes on usage handling of source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin) and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 m f 0.1 m f is recom- mended.
45/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge v cc v ss v ref av ss v ia v ih v ih v ih v ih v ih v ih v il v il v il v il v il electrical characteristics table 11 absolute maximum ratings power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , v ref input voltage p2 2 , p2 3 input voltage reset, x in input voltage cnv ss output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , x out output voltage p2 2 , p2 3 power dissipation operating temperature storage temperature v cc v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings C0.3 to 6.5 C0.3 to v cc +0.3 C0.3 to 5.8 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 5.8 300 C20 to 85 C40 to 125 v v v v v v v mw c c unit t a = 25 c all voltages are based on v ss . output transistors are cut off. 5.5 5.5 v cc v cc v cc 5.8 v cc 5.8 v cc v cc 0.2v cc 0.3v cc 0.6 0.2v cc 0.16v cc power source voltage (at 8 mhz) power source voltage (at 4 mhz) power source voltage a-d convert reference voltage analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 h input voltage (when i 2 c-bus input level is selected) sda 1 , scl 1 h input voltage (when i 2 c-bus input level is selected) sda 2 , scl 2 h input voltage (when smbus input level is selected) sda 1 , scl 1 h input voltage (when smbus input level is selected) sda 2 , scl 2 h input voltage reset, x in , cnv ss l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 l input voltage (when i 2 c-bus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 l input voltage (when smbus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 l input voltage reset, cnv ss l input voltage x in symbol parameter limits min. v v v v v v v v v v v v v v v v unit table 12 recommended operating conditions (1) (v cc = 2.7 to 5.5 v, t a = C20 to 85 c, unless otherwise noted) 4.0 2.7 2.0 av ss 0.8v cc 0.7v cc 0.7v cc 1.4 1.4 0.8v cc 0 0 0 0 0 5.0 5.0 0 0 typ. max. C80 C80 80 80 80 C40 C40 40 40 40 h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 7 (note) h total peak output current p2 0 , p2 1 , p2 4 Cp2 7 , p4 0 Cp4 7 (note) l total peak output current p0 0 Cp0 7 , p3 0 Cp3 7 (note) l total peak output current p1 0 Cp1 7 (note) l total peak output current p2 0 Cp2 7 ,p4 0 Cp4 7 (note) h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 7 (note) h total average output current p2 0 , p2 1 , p2 4 Cp2 7 , p4 0 Cp4 7 (note) l total average output current p0 0 Cp0 7 , p3 0 Cp3 7 (note) l total average output current p1 0 Cp1 7 (note) l total average output current p2 0 Cp2 7 ,p4 0 Cp4 7 (note) s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) s i ol(avg) ma ma ma ma ma ma ma ma ma ma note : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents.
46/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge table 13 recommended operating conditions (2) (v cc = 2.7 to 5.5 v, t a = C20 to 85 c, unless otherwise noted) C10 h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1 , p2 4 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 (note 1) l peak output current p0 0 Cp0 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 (note 1) l peak output current p1 0 Cp1 7 (note 1) h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1 , p2 4 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 (note 2) l average output current p0 0 Cp0 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 (note 2) l peak output current p1 0 Cp1 7 (note 2) internal clock oscillation frequency (v cc = 4.0 to 5.5v) (note 3) internal clock oscillation frequency (v cc = 2.7 to 5.5v) (note 3) i oh(peak) symbol parameter limits min. ma unit typ. max. notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50%. i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) f(x in ) 10 20 C5 5 8 4 15 ma ma ma ma ma mhz khz
47/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge table 14 electrical characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 (note) l output voltage p0 0 Cp0 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 l output voltage p1 0 Cp1 7 hysteresis cntr 0 , cntr 1 , int 0 Cint 3 hysteresis rxd, s clk hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 h input current reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 p3 0 Cp3 7 , p4 0 Cp4 7 l input current reset,cnv ss l input current x in ram hold voltage limits v v v v v v parameter min. typ. max. symbol unit note: p2 5 is measured when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. i oh = C10 ma v cc = 4.0C5.5 v i oh = C1.0 ma v cc = 2.7C5.5 v i ol = 10 ma v cc = 4.0C5.5 v i ol = 1.0 ma v cc = 2.7C5.5 v i ol = 20 ma v cc = 4.0C5.5 v i ol = 10 ma v cc = 2.7C5.5 v v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss v i = v ss when clock stopped v cc C2.0 v cc C1.0 test conditions 0.4 0.5 0.5 2.0 1.0 2.0 1.0 v oh v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i ih i ih i il i il i il v ram 2.0 4 C4 5.0 5.0 C5.0 C5.0 5.5 v v v m a m a m a m a m a m a v
48/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge table 15 electrical characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off middle-speed mode f(x in ) = 8 mhz f(x cin ) = stopped output transistors off middle-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = stopped output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz test conditions 13 i cc ta = 25 c ta = 85 c 6.8 ma all oscillation stopped (in stp state) output transistors off 1.6 60 20 20 5.0 4.0 1.5 800 0.1 200 40 55 10.0 7.0 1.0 10 ma m a m a m a m a ma ma m a m a m a
49/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge bit lsb tc( f ) m s k w m a m a m a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 50 typ. 40 35 150 0.5 max. 10 4 61 200 5 5.0 high-speed mode, middle-speed mode low-speed mode v ref = 5.0 v table 16 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = C20 to 85 c, f(x in ) = 8 mhz, unless otherwise noted) unit limits parameter C C t conv r ladder i vref i i(ad) test conditions symbol v ref on v ref off
50/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge timing requirements table 17 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 clock input set up time serial i/o1 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input set up time serial i/o2 clock input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 typ. max. symbol unit note : when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). table 18 timing requirements (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 clock input set up time serial i/o1 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input set up time serial i/o2 clock input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 typ. max. symbol unit note : when f(x in ) = 4 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart).
51/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge table 19 switching characteristics 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2C30 t c (s clk1 )/2C30 C30 t c (s clk2 )/2C160 t c (s clk2 )/2C160 0 typ. 10 10 max. 140 30 30 200 30 30 30 symbol unit notes 1: for t wh (s clk1 ), t wl (s clk1 ), when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: when the p0 1 /s out2 and p0 2 /s clk2 p-channel output disable bit of the serial i/o2 control register (bit 7 of address 0015 16 ) is 0. 3: the x out pin is excluded. table 20 switching characteristics 2 (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2C50 t c (s clk1 )/2C50 C30 t c (s clk2 )/2C240 t c (s clk2 )/2C240 0 typ. 20 20 symbol unit notes 1: for t wh (s clk1 ), t wl (s clk1 ), when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: when the p0 1 /s out2 and p0 2 /s clk2 p-channel output disable bit of the serial i/o2 control register (bit 7 of address 0015 16 ) is 0. 3: the x out pin is excluded. max. 350 50 50 400 50 50 50 test conditions fig. 53 test conditions fig. 53
52/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge measurement output pin 100pf cmos output fig. 53 circuit for measuring output switching characteris- tics
53/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge fig. 54 timing diagram t c(cntr) 0.2v cc t wl(int) 0.8v cc t wh(int) 0.2v cc 0.8v cc t w(reset) reset 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t wl(x in ) 0.8v cc t wh(x in ) t c(x in ) x in t f t r t d(s clk1 -t x d), t d(s clk2 -s out2 ) t v(s clk1 -t x d), t v(s clk2 -s out2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) t h(s clk1 - r x d), t h(s clk2 - s in2 ) t su(r x d - s clk1 ), t su(s in2 - s clk2 ) t x d s out2 r x d s in2 s clk1 s clk2 int 0 to int 3 cntr 0 cntr 1
54/54 m37516m6-xxxhp gnok-m37516m6-xxxhp-50 (msetsu 2) pa ge symbol parameter unit multi-master i 2 c-bus bus line characteristics table 21 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition hold time for scl clock = 0 rising time of both scl and sda signals data hold time hold time for scl clock = 1 falling time of both scl and sda signals data setup time setup time for repeated start condition setup time for stop condition t buf t hd;sta t low t r t hd;dat t high t f t su;dat t su;sta t su;sto min. max. min. max. m s m s m s ns m s m s ns ns m s m s standard clock mode high-speed clock mode note: c b = total capacitance of 1 bus line fig. 55 timing diagram of multi-master i 2 c-bus 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 300 0.9 300 t buf t hd:sta t hd:dat t low t r t f t high t su:dat t su:sta t hd:sta t su:sto scl p s sr p sda s : start condition sr : restart condition p : stop condition

▲Up To Search▲

Price & Availability of M37516M6-A05

	To Download M37516M6-A05 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .